'EBNF'에 해당되는 글 2건
- 2009.04.03
- 2009.04.03
module counter;
integer R;
initial
for (R=1; R <= 10; R = R + 1)
$display ("R= %d", R);
endmodule
dlsplay_statement ::= $display; I $display ( <arguments> );
write_statement ::= $write; I $write ( <arguments> );
arguments ::= <argument> | <argument>, <arguments>
argument ::= "<string>" I <expression>
\n New line Quotation
\t Tabulator
\\ Character\
\"
%% mark Character %
%h, %H Hexadecimal number
%d, %D Decimal number
%o, %O Octal number
%b, %B Binary number
%f, %F Real number
%c Single character
%s Character string
%t Time
%m Present module name
그럼 이제 Verilog 프로그램과 module에 대한 EBNF를 살펴보고 마치도록 한다.
VERILOG program ::= <module> I <VERILOG_program> <module>
module ::= module <name_of_module> <list of ports>;
<module item>
endmodule
name_of_module ::= <identifier>
list of ports ::= I ( <port_list> )
port_list ::= <identifier> I <port_list> , <port_list>
module_item ::= <parameter_declaration> I <input_declaration>
I <output declaration> | <inout declaration>
I <reg_declaration> I <integer_declaration> | <wire_declaration>
I <event_declaration> I <gate_instantiation>
I <module_instantiation> | <always_statement>
| <initial_statement> | <continuous_assign> I <function>
I <task> I <module_item> <module item>
module_instantiation ::= <type_of_module>
<name_of_instance> ( <module arguments> );
for_loop ::= FOR <variable>:=<number> TO <number> <stepsize> DO
<statement>;
Variable ::= <variable> <variable> I <digit> I a I b I c I d I e I f I g I h
I i I j I k | l I m I n I o I p I q I r I s I t I u I v I w I x
I y I z I A I B I C I D I E I F I G I H I I I J I K I L I M I N
I O I P I Q I R I S I T I U I V I W I X I Y I Z
stepsize ::= I STEP <number>